A Low-Power SRAM Using Bit-Line Charge-Recycling
نویسندگان
چکیده
منابع مشابه
A low-power SRAM using bit-line charge-recycling
Permanent magnet and wound rotor synchronous machines (PMSMs and WRSMs) are often used in diesel enginebased portable power generation systems. In these applications, there is a growing desire to improve machine efficiency in order to reduce fossil fuel requirements. In addition, there is a desire to reduce mass to improve mobility. To attempt to address these competing performance objectives, ...
متن کاملA Design of Sram Structure for Low Power Using Heterojunction Cmos with Single Bit Line
The Present day workstations, low-power processors, computers and super computers are using fast Static Random Access Memory (SRAMs) and will require, in the future, larger density memories with faster access time and minimum power consumption. Acknowledging the intense requirements for power, in current high performance memories of computing devices, the circuit designers have developed a numb...
متن کاملA low power charge-recycling ROM architecture
A new low power charge recycling ROM (CR-ROM) architecture is proposed. The CR-ROM uses charge-recycling method [4] in bit lines of ROM to save the power consumption. About 90% of the total power used in the ROM is consumed in bit lines [1]. With the proposed method, power consumption in ROM bit lines can be reduced asymptotically to zero if the number of bit lines is infinite and the sense amp...
متن کاملA low power charge sharing ROM using dummy bit lines
This paper proposes a shared-capacitor charge-sharing ROM (SCCS-ROM). The SCCS-ROM reduces the swing voltage using the charge-sharing technique of the charge-sharing ROM (CSROM) [4]. Although the CS-ROM needs three small capacitors per output, the SCCS-ROM shares the capacitors so that it needs only three capacitors. The SCCS-ROM implements the capacitors using dummy bit lines. This not only in...
متن کاملA 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation
This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y -access MOS (column-direction access transistor) can improve dummy-read cells’ noise margin and isolate the pre-charge noise from bit-lines in synchronous ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Journal of Solid-State Circuits
سال: 2008
ISSN: 0018-9200,1558-173X
DOI: 10.1109/jssc.2007.914294